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NXP Semiconductors /LPC800 /PIN_INT /IENR

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Interpret as IENR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0ENRL0RESERVED

Description

Pin interrupt level or rising edge interrupt enable register

Fields

ENRL

Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt.
RESERVED

Reserved.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data